🚀 go-pugleaf

In article <19913@obiwan.mips.COM> mark@mips.COM (Mark G. Johnson) writes:
>     "It's not nearly as much fun building a supercomputer as it is
>      simply inventing one" --- N. Lincoln

>[semiconductor manufacturers would] much rather listen to the 
>Big Company Purchasing Agent than
>the pontificating idea-man who claims to know what the future demand
>might be.  At least the purchasing agent can deliver, WITH CERTAINTY,
>a large market.

I was at DEC long enough to know the other side of this issue as well.
They tend to be VERY conservative about bringing new components and
technologies in-house.  Much of this is due to a history of being
burned; designing it in, then having the manufacturer bag out.  These
cases are what tends to be remembered, not the supplier uneventfully
delivering on time.  In terms of what makes it into the urban legend
notebook, anyway.

In other words, don't plan on going to a larger company to decide on
innovative new products.

In fact, they tend to push too hard even when considering new
technologies.  In doing gate array designs, for example, there is a
chance, however small, that a chip can't be laid out and still meet
the performance predicted by the design manual.  When I was there
anyway, they demanded that manufacturers prove that they can guarantee
that that wouldn't happen, with sizeable punitive measures if it
did.  I didn't blame them when they walked away from the business.

At Alliant, we had a much more liberal attitude.  In fact, that's why
I think a lot of startups start up; the large companies being slow to
adapt new stuff creates a real niche for risk-takers using the hot
chips.  Some fail because their hot chips don't show up.


>However, semiconductor companies will occasionally be daring and try
>something new & different.  And, for the most part, they've gotten a
>bloody nose for their troubles.
>
>Four or five years ago the rage was "intelligent memories".  It was...
>
>Next came cache-Tag RAMs.  Boy howdy, aren't these what the world
>needed...

Unfortunately, the cache-tag guys screwed up.  They insisted on using
technology n-1.  You could always make a faster cache using vanilla
technology n RAMs.  Really, if you're going to make asic memories work,
you have to use the hottest process.  Or have a very substantial
"value added" in some other dimension.

Warning:  Anecdote following.  "Type 'n' now"
I remember trying to convince reps from semi houses that they should
make an edge-triggered SRAM; they could do away with the
address-line-change detector circuits, and have a dandy edge to start
the timing chain, and we would have a faster RAM with a built-in
address register.  The response?  "Shut up, you're a system designer.
You don't know anything about RAM's."  We even could never convince them
that you don't need a cycle time equal to access time!
-Stan