🚀 go-pugleaf

In article <744@cirrusl.UUCP> grenley@sunkist (George Grenley) writes:
>In article <40106@bbn.COM> slackey@BBN.COM (Stan Lackey) writes:
>>I remember trying to convince reps from semi houses that they should
>>make an edge-triggered SRAM; they could do away with the
>I worked at Mostek in the early eighties; at that time they made a line 
>of edge triggered (CS*) SRAMs and ROMs - state of the art in speed
>and density, too (for the time).

I think I remember this one.  If it had had an address register, it
would have been perfect.  That's how you get away with requiring a
clock.  Of course, you need to supply this version in addition to the
vanilla stuff, not in place of, for the 3 or 4 "stuck in their ways"
designers out there.  And all the applications that really do need a
fully static RAM.

>>We even could never convince them
>>that you don't need a cycle time equal to access time!
>The market SCREAMED for access time = cycle time, no clocking required,

Well, if someone can show me a circuit that reliably cycles static,
registerless RAM's at their access time, I know a LOT of engineers who
would like to see it.  (Not a tester, please.)  I suspect the
"screaming" was done by people who didn't understand the issues; they
may not have understood what you were talking about, were suspicious,
and reacted in an emotional manner.  Not something I would ever do. :-)

A high speed instruction cache for a RISC could be a target for
this kind of chip: it clocks in the prefetch address, and accesses the
instruction in say 15ns.  It has the time spent passing the
instruction into the data path chip(s) to precharge, or whatever a RAM
chip might do, for the next access.  Thus, if the system clocks at
25ns, the access time is 15ns, the cycle time is slower than the
access time, and everthing's great. :-)
-S.A.L.