🚀 go-pugleaf

in article <27133@proton.mips.COM>, wilkes@mips.COM (John Wilkes) says:
> 
> In article <7851@cbmvax.UUCP> daveh@cbmvax.UUCP (Dave Haynie) writes:

>>MUST between user tasks, since the address spaces are aliased.  Caching still

> i believe that this is true only for a virtual cache.  a physical cache
> does not have the aliasing problem.

Yup, I thought of that later.  Guess I'm used to virtual caches.  However, it
may not make much difference anyway.  You are guaranteed under today's UNIX
at least that two tasks won't be sharing any memory.  So whatever's cached up
by one task is on the chopping block as soon as you switch, and it's not going
to do any good, even if it's not overwritten, until the original task gets
swapped back in.  Especially since most of the external caches tend to be 
direct mapped.  Some of the new chips with cool 4 set associative physical 
caches ('040, 88k) might make this a bit more interesting.

>>> Harvard A.(separate data/instruction cache), 

>>This isn't an advantage as an external cache unless you're CPU has external
>>I and D busses.  The only one I know of that does is the Motorola 88100.  While

> not necessarily.  you might want your d cache to have a 128-byte line, and
> your i cache to have an eight byte line, for example.  code references and
> data references usually have different access patterns.

Well, that's true.  You may also decide that it's more efficient to have an I
cache of size M and a D cache of size N than a unified cache, depending on 
the system.

> doesn't the amd 29000 have external i and d busses?  it's been a long time
> since i looked at that chip...

Bingo!  While they share a common set of address lines, the 29K does have 
separate data paths for I and D caches.  It's been awhile for me too, but 
the 29K is a neat chip.

> -wilkes
-- 
Dave Haynie Commodore-Amiga (Systems Engineering) "The Crew That Never Rests"
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