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Subject: Wait-states on 8051
Newsgroups: sci.electronics,comp.arch
Keywords: Wait states, 8051, 80C152

Hello,

I'm building a 80C152 based board ( the 80C152 is a member of the 8051 family,
which includes a synchronous serial port in addition to the standard async
serial port. it also adds DMA support for both ports, and 1-3 additional
ports ( P4, and P5-6 depending on the specific 80C152 model ).

My board has dual 80C152's sharing a common dual-port memory ( Am2130 ).
I have to add a wait state to one of the processors when both processors
access the same address at the same time ( according to the ~BUSY line
which comes from the Am2130 ).

I have no idea how to add wait states to the 80C152, since the bus is
synchronous ( i.e. it has only a ~RD or ~WR line, which are low for
a fixed amount of time, unlike the 68000, for example, which has a ~DTACK
line which 'tells' the processor when the memory is ready ).

Can I do this with the 80C152? Or does an irregular clock has any negative
affects on the processor? I'm currently using the built in oscillator ( with
only an external crystal and 2 caps ), and I would prefer not building an
external clock generator if it isn't necessary.

Please answer by mail, since our news system isn't very reliable in the last
few weeks. I'll post a summary later..

thanks in advance,
Udi
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