Article View: comp.arch
Article #2199Re: How Caches Work
From: John D. McCalpin
Date: Tue, 12 Sep 1989 15:12
Date: Tue, 12 Sep 1989 15:12
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In message <3989@phri.UUCP> roy@phri.UUCP (Roy Smith) writes: >Here's a (possibly crazy) idea for cache design. The current EUD >(Example Under Debate) shows that caches just don't work for sequential >access, but we knew that already. [ Roy describes a system for which only a portion of the address space is sun through the cache ] > So what do you think? Has this been done before? Along a similar line, the Convex machines cache accesses going to the scalar unit only. The load/store unit for the vector unit operates directly from main memory to the vector registers. This is pretty close to what Roy describes, but it is not controlled by any tags, merely by which functional unit executes the load instruction. -- John D. McCalpin - mccalpin@masig1.ocean.fsu.edu mccalpin@scri1.scri.fsu.edu mccalpin@delocn.udel.edu
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Path: arc1-ca.pugleaf.net!utzoo!attcan!utgpu!jarvis.csri.toronto.edu!mailrus!ames!rex!uflorida!stat!stat.fsu.edu!mccalpin From: mccalpin@masig3.ocean.fsu.edu (John D. McCalpin) Newsgroups: comp.arch Subject: Re: How Caches Work Message-ID: <MCCALPIN.89Sep12111256@masig3.ocean.fsu.edu> Date: 12 Sep 89 15:12:56 GMT References: <21936@cup.portal.com> <1082@cernvax.UUCP> <16306@watdragon.waterloo.edu> <RANG.89Sep10184900@derby.cs.wisc.edu> <8399@boring.cwi.nl> <3989@phri.UUCP> Sender: news@stat.fsu.edu Organization: Supercomputer Computations Research Institute Lines: 21 In-reply-to: roy@phri.UUCP's message of 12 Sep 89 14:11:23 GMT