Article View: comp.arch
Article #2200Re: SRAM vs. DRAM, 33MHz 386 UNIX-PC
From: Robert Firth
Date: Mon, 11 Sep 1989 20:17
Date: Mon, 11 Sep 1989 20:17
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1106 bytes
In article <1082@cernvax.UUCP> hjm@cernvax.UUCP (Hubert Matthews) writes: > SUM = 0.0 > DO 10 I = 1, 1000000 > SUM = SUM + VEC(I) > 10 CONTINUE > >A data cache is *no use at all* for this problem. I don't see that. Suppose the first reference causes a cache miss. The machine then fetches a chunk of data from memory - 32 bytes, say. The next reference finds the data in the cache, and runs right along. If we assume double-precision FP at 8 bytes per datum, we have a 75% cache hit rate. Not stellar, but still pretty good. Did you mean to write SUM = SUM + MAT(I,J) varying J? That, I grant, is a tough one.
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Path: arc1-ca.pugleaf.net!utzoo!attcan!utgpu!jarvis.csri.toronto.edu!mailrus!tut.cis.ohio-state.edu!pt.cs.cmu.edu!sei!firth From: firth@sei.cmu.edu (Robert Firth) Newsgroups: comp.arch Subject: Re: SRAM vs. DRAM, 33MHz 386 UNIX-PC Message-ID: <4071@bd.sei.cmu.edu> Date: 11 Sep 89 20:17:16 GMT References: <21936@cup.portal.com> <1082@cernvax.UUCP> Reply-To: firth@sei.cmu.edu (Robert Firth) Organization: Software Engineering Institute, Pittsburgh, PA Lines: 20