Article View: comp.arch
Article #22146Re: RISC Machine Data Structure Word Alignment Problems?
From: Rob Peglar
Date: Fri, 02 Feb 1990 20:31
Date: Fri, 02 Feb 1990 20:31
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1652 bytes
In article <4YG1638xds13@ficc.uu.net>, peter@ficc.uu.net (Peter da Silva) writes: > In article <3428@odin.SGI.COM> pkr@maddog.sgi.com (Phil Ronzone) writes: > > No, I disagree. Most of the time the data (mis)alignments are from real world > > constraint. Compressed video data, even when capacious CD-ROMs are used, are > > full of adjacent 1, 2, 3, and 4 byte integer > > And ajacent 4-, 5-, 6-, and 12- bit integers as well. I've heard of bit > addressible memory, but outside of microcontrollers I've never actually > seen it. > Actually, since the days of the CDC Star-100, that particular line of supercomputers (Star-Cy 203-Cy 205-ETA10) supported bit-addressable memory. This was important for things like vector bit string operations on arbitrary aligned operands. Such things (bit vector C <- bit vector A && bit vector B) were in microcode. Just thought you'd like to know. Rob -- Rob Peglar Control Systems, Inc. 2675 Patton Rd., St. Paul MN 55113 ...uunet!csinc!rpeglar 612-631-7800 The posting above does not necessarily represent the policies of my employer.
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Path: arc1-ca.pugleaf.net!utzoo!utgpu!jarvis.csri.toronto.edu!rutgers!usc!zaphod.mps.ohio-state.edu!uakari.primate.wisc.edu!aplcen!uunet!csinc!rpeglar From: rpeglar@csinc.UUCP (Rob Peglar) Newsgroups: comp.arch Subject: Re: RISC Machine Data Structure Word Alignment Problems? Summary: bit addressable memory architecture example Message-ID: <165@csinc.UUCP> Date: 2 Feb 90 20:31:19 GMT References: <111@melpar.UUCP> <1990Jan21.224826.1699@esegue.segue.boston.ma.us> <4YG1638xds13@ficc.uu.net> Organization: Control Systems, Inc., St. Paul MN Lines: 25