🚀 go-pugleaf

In article <6998@celit.fps.com> ps@fps.com (Patricia Shanahan) writes:
>In article <29718@brunix.UUCP> phg@cs.brown.edu (Peter H. Golde) writes:
>>One might note that implementing a 64-bit address space
>>with 64 KB pages and 8 bytes/page in the page table requires
>>2 billion megabytes of page-table space.  Hmmmmm.....
>If the real memory is small compared to the address space, don't use page
>tables. If you must use page tables, design them as sparse arrays.

1) Several posters have mentioned that there is some unspecified but obvious
(to them) major problem with using inverted page tables together with
memory mapped files.  I wonder if someone could enlighten us regarding
this problem, since apparently it isn't obvious to every system architect :-)

2) It isn't apparent to me that page size is really a function of physical
memory size so much as it is of processing speed.  It might be noted that
the Cyber 205, which had virtual memory and vector processing, used two
page sizes, because potentially the system ate through memory at a rate of
about one new page every 512/3 clock cycles average with "small" (4 KByte)
pages.  Associative register (~TLB) misses cost, on that system, ~150 CPU
cycles, so the overhead was high enough that it was worth it to add
large pages (512 KBytes).  But, if you can keep the overhead on a TLB miss
down, I see no reason why you need larger pages.  Does anyone have any
hard data on how many clock cycles are chewed up on TLB misses on recent
RISC systems? 


  Hugh LaMaster, m/s 233-9,  UUCP ames!lamaster
  NASA Ames Research Center  ARPA lamaster@ames.arc.nasa.gov
  Moffett Field, CA 94035     
  Phone:  (415)694-6117