Article View: comp.arch
Article #22640Question on multiprocessor bus/mem speed
From: tam
Date: Tue, 27 Feb 1990 04:46
Date: Tue, 27 Feb 1990 04:46
23 lines
1449 bytes
1449 bytes
If you have the information, please help answer the following
questions for ONE or MORE of these commercial multiprocessors
(Sequent Balance, Sequent Symmetry, Encore Multimax, Alliant FX/8):
1. Processor used (name/model) & clock speed of processor (in MHz)
2. Bus cycle time (in MHz).
3. Cache read/write access time (in nano-seconds)
4. Main memory read/write access time (in nano-seconds)
5. Typical cache miss delay (in nano-seconds)
Please indicate if there are multiple answers to each question.
Also, specific references (publications & reports) for these systems
are requested.
Besides getting the exact numbers for each part, the general idea
behind these questions is to understand the relative speeds of
processor, cache, bus, and memory of the shared memory bus-based
multiprocessor systems.
Please send e-mail to tam@vega.berkeley.edu. I will post the collected
reponses. Thanks a mega for your time.
<-- Tam M. Nguyen --> { tam@ernie.Berkeley.EDU | ...!ucbvax!ucbernie!tam }
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Path: arc1-ca.pugleaf.net!utzoo!utgpu!jarvis.csri.toronto.edu!cs.utexas.edu!uwm.edu!ogicse!ucsd!helios.ee.lbl.gov!pasteur!vega.uucp!tam From: tam@vega.uucp Newsgroups: comp.arch Subject: Question on multiprocessor bus/mem speed Message-ID: <22451@pasteur.Berkeley.EDU> Date: 27 Feb 90 04:46:40 GMT Sender: news@pasteur.Berkeley.EDU Reply-To: tam@vega.uucp () Organization: University of California at Berkeley Lines: 23