🚀 go-pugleaf

In article <BBC.90Feb25195510@legia.rice.edu> Benjamin Chase <bbc@rice.edu> writes:
>Perhaps in the floating point slot of the superscalar instruction,
>you'd put (among other things?) little hints to the cache instead?
>Whisper gently into the processor's ear, saying "get the value in
>register N, and use that as a stride for yanking words into the cache
>until I tell you something different".

	This idea exists (though not in superscalar form) in the RPM-40
cache and coprocessor design.  The cache control appears to the processor
as a logical coprocessor.  You can fill pipeline interlocks, load delays,
etc with cache setup/hint instructions.  The RPM-40 had lines going to the
cache to tell it which register (if any) a load/store was relative to, which
could be used by the cache to act differently according to register number.

	For example, access relative to register 1 might be sequential,
relative to register 2 might skip X words on each access, register 3 might
have random access habits, etc. (there were a couple of other things about it
you could control also).  For I-Cache, you could control how many entries of
the Branch-Target-Cache (BTC) were handled by LRU, and how many the software
wanted to provide the addresses to cache.

-- 
Randell Jesup, Keeper of AmigaDos, Commodore Engineering.
{uunet|rutgers}!cbmvax!jesup, jesup@cbmvax.cbm.commodore.com  BIX: rjesup  
Common phrase heard at Amiga Devcon '89: "It's in there!"