🚀 go-pugleaf

In article <73ro0u$j8t$1@winter.news.rcn.net>, 
SpamYourselFtwest@agora.rdrop.kom says...

[ ... ] 

> That's funny; rdtsc is not in any instruction set listing for the K5,
> K6, MediaGX, MII, or WinChip I've ever seen, including ones from AMD,
> Cyrix, and IDT.  If they're too lazy to complete their manuals within a
> year of shipping a part, that's not my fault.  Even close-mouthed Intel
> manages that.  ;-)

You're mistaking lack of proof of existence for proof of lack of 
existence -- your statement was NOT that you didn't know whether it 
existed, but that it did NOT exist.

Testing on actual chips proves that your statement was false.
 
> I would also argue that ring 0 read model specific register and read
> performance counter instructions are not compatible, as rdtsc is a ring
> 3 instruction.  

If that were the case, you'd be correct.  However, RDTSC (using 
exactly the same binary as on an Intel chip) works perfectly well in 
ring 3 on an AMD chip, for one that I've tested with.

> Likewise, I don't think the "undocumented" ways of
> sneaking into the performance registers really count either---it's not
> like you can bit test and know they'll work, as you can with rdtsc (at
> least on an Intel part).  I, for one, have better things to do with my
> time than guessing what instructions an x86 processor supports.

Read my lips if necessary: NO undocumented instructions.  Binaries 
written for an Intel chip using RDTSC work perfectly well on other 
chips as well.  I have personally verified that it works on AMD K6 and 
K6-2 chips. (among several others...)