🚀 go-pugleaf

SpamYourselFtwest@agora.rdrop.kom says...
> Paul Hsieh <qed@pobox.com> wrote:
> >That's not correct.  All modern x86 CPUs have a functioning/compatible 
> >RDTSC instruction.
> 
> That's funny; rdtsc is not in any instruction set listing for the K5,
> K6, MediaGX, MII, or WinChip I've ever seen, including ones from AMD,
> Cyrix, and IDT.

WinChip, 6x86MX/MII, K5 and all K6's have RDTSC.  I don't know about the 
MediaGX.

> [...]  If they're too lazy to complete their manuals within a
> year of shipping a part, that's not my fault.  Even close-mouthed Intel
> manages that.  ;-)

There is no good manual on x86 instruction set compatibility that I know 
of.  Nevertheless, if you have a good one it should document the CPUID 
instruction which you can test function 1, bit 4 of edx.  That's how you 
know whether or not your CPU supports the TSC register.
 
> I would also argue that ring 0 read model specific register and read
> performance counter instructions are not compatible, as rdtsc is a ring
> 3 instruction.

RDTSC operates in all rings; It does not run in 16 bit v86 mode.

> [...] Likewise, I don't think the "undocumented" ways of
> sneaking into the performance registers really count either---it's not
> like you can bit test and know they'll work, as you can with rdtsc (at
> least on an Intel part).  I, for one, have better things to do with my
> time than guessing what instructions an x86 processor supports.

You don't have to guess.  Use the CPUID instruction above -- it tells you 
all the additional features that your processor supports.
 
> FWIW, I've also had invalid opcode faults on rdtsc on an early K6,

Impossible.  Unless you are in 16 bit v86 mode (ask Intel about that.)

--
Paul Hsieh
qed@pobox.com