🚀 go-pugleaf

Paul Hsieh <qed@pobox.com> wrote:
>That's not correct.  All modern x86 CPUs have a functioning/compatible 
>RDTSC instruction.

That's funny; rdtsc is not in any instruction set listing for the K5,
K6, MediaGX, MII, or WinChip I've ever seen, including ones from AMD,
Cyrix, and IDT.  If they're too lazy to complete their manuals within a
year of shipping a part, that's not my fault.  Even close-mouthed Intel
manages that.  ;-)

I would also argue that ring 0 read model specific register and read
performance counter instructions are not compatible, as rdtsc is a ring
3 instruction.  Likewise, I don't think the "undocumented" ways of
sneaking into the performance registers really count either---it's not
like you can bit test and know they'll work, as you can with rdtsc (at
least on an Intel part).  I, for one, have better things to do with my
time than guessing what instructions an x86 processor supports.

FWIW, I've also had invalid opcode faults on rdtsc on an early K6,
though I suppose it could have been yet another bad AMD part, like the
non-overclocked 486 I had which fried itself after a piddly 18 months of
uptime.

Todd

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