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Article #2737Re: ERISC???
From: Anton Rang
Date: Sat, 21 Oct 1989 03:08
Date: Sat, 21 Oct 1989 03:08
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1440 bytes
In article <126596@sun.Eng.Sun.COM> khb%chiba@Sun.COM (Keith Bierman - SPD Advanced Languages) writes: >>2. All instructions (operations) consume a single processor cycle with the >> possible exceptions of LOAD and STORE. > >I know of NO machine which performs single floating point OPS in 1 >cycle (some machines can achieve 1 fop/cycle when the pipes can be >kept full). Are there counterexamples, or is #2 simply at variance >with reality ? Lots of RISC systems implement floating-point using a coprocessor which runs asynchronously with the main (integer) processor. I think the idea here is not to let slow floating-point operations slow down the integer pipeline (but I could be wrong). Anton +----------------------------------+------------------+ | Anton Rang (grad student) | rang@cs.wisc.edu | | University of Wisconsin--Madison | | +----------------------------------+------------------+
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Path: arc1-ca.pugleaf.net!utzoo!utgpu!jarvis.csri.toronto.edu!mailrus!uwm.edu!uwvax!rang From: rang@cs.wisc.edu (Anton Rang) Newsgroups: comp.arch Subject: Re: ERISC??? Message-ID: <RANG.89Oct20220859@derby.cs.wisc.edu> Date: 21 Oct 89 03:08:59 GMT References: <1989Oct19.155752.13028@mentor.com> <126596@sun.Eng.Sun.COM> Sender: news@spool.cs.wisc.edu Distribution: usa Organization: UW-Madison CS department Lines: 20 In-reply-to: khb%chiba@Sun.COM's message of 20 Oct 89 16:55:05 GMT