Article View: comp.arch
Article #2891On-chip/ Off-chip Cache
From: Jayashree Ramanathan
Date: Mon, 30 Oct 1989 20:36
Date: Mon, 30 Oct 1989 20:36
24 lines
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1306 bytes
I am looking for references that discuss on-chip, off-chip caches. I am interested in the following characteristics: What are the typical sizes as of now ? What is the relative size increase every year due to technology improvements? Placement/replacement policies to manage these caches Is the organization/management of these two caches independent? If not, in what way do they affect each other? Any pointers will be appreciated. Thanks, Jayashree ----------------------------------------------------------------------------- Jayashree Ramanathan E-mail: Graduate Assistant jaya@cpsvax.cps.msu.edu (ARPAnet and CSnet) Dept. of Computer Science jaya@msuegr.BITNET Michigan State University uunet!frith!jaya East Lansing MI48824 -----------------------------------------------------------------------------
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arc1-ca.pugleaf.net!utzoo!attcan!utgpu!jarvis.csri.toronto.edu!mailrus!iuvax!ux1.cso.uiuc.edu!tank!eecae!cps3xx!cpsvax!jayaShow Full Headers
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Path: arc1-ca.pugleaf.net!utzoo!attcan!utgpu!jarvis.csri.toronto.edu!mailrus!iuvax!ux1.cso.uiuc.edu!tank!eecae!cps3xx!cpsvax!jaya From: jaya@cpsvax.cps.msu.edu (Jayashree Ramanathan) Newsgroups: comp.arch Subject: On-chip/ Off-chip Cache Message-ID: <5183@cps3xx.UUCP> Date: 30 Oct 89 20:36:01 GMT Sender: usenet@cps3xx.UUCP Reply-To: jaya@cpsvax.cps.msu.edu (Jayashree Ramanathan) Organization: Michigan State University, Computer Science Department Lines: 24