🚀 go-pugleaf

In article <AGLEW.89Oct27193246@chant.urbana.mcd.mot.com> aglew@urbana.mcd.mot.com (Andy-Krazy-Glew) writes:

>Can you provide any references or publications on these designs?

This is information which I gathered from reading hardware reference manuals
supplied by the mfrs. during courses they taught on-site at Ames.  I find it
an interesting architectural tradeoff that, generally, CDC was able to deliver
better results/clock cycle  numbers, but Cray could deliver sufficiently
better clock cycles :-)  How much of this was Cray himself, and how much of it
was the fact that there were significantly more gates in the CDC design, is 
open to speculation.  That is, in fact, why I looked at the number of gates.
Only the broad description (250,000 5/4 NAND gates - type information) is
available in these publications, however.  I think you would have to kill
someone to get the actual layouts.

>>The first increment of improvement could come about by segmenting

>What do you mean by "segmenting"?  Do you mean pipelining - eg. so that

Yes, I mean pipelining.  

>IEEE extended (80 bit)
>division in 4 cycles.

This does indeed sound interesting.  One would need to know how many gate
delays per stage there are, though, to be really exciting.

>rounding.  Ie. it is ROUND(A*B+C).  This is "more accurate" but does
>not necessarily produce the same answers as ROUND(ROUND(A*B)+C).
>I wonder what the numerical analysis mavens have to say about this:

At least ONE Numerical Analyst  ( :-) seem to dislike this.  The "Paranoia"
benchmark, available from netlib, requires intermediate results to be
exactly 64 bit precision for a perfect score.

  Hugh LaMaster, m/s 233-9,  UUCP ames!lamaster
  NASA Ames Research Center  ARPA lamaster@ames.arc.nasa.gov
  Moffett Field, CA 94035     
  Phone:  (415)694-6117