🚀 go-pugleaf

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>In article <31149@winchester.mips.COM> mash@mips.COM (John Mashey) writes:
> In article <blah blah> Allen Baum says:
>>Ah, yes. I think its safe to say that our simple RISCs are going to start to
>>get fairly complex, as we start to play all the little hardware tricks we've
>>known from the supercomputer world, and some that we'll invent. Note that a
>>lot of errors come from exception handling kinds of problems, and while CISC
>>machines have them, superscalar, out-of-order execution RISC machines will
>>have them in spades.

>Yes, but superscalar, out-of-order CISCs would have them in spades&hearts :-)
>
>The new IBM stuff looks interesting....

I guess what I was trying to say is that I think its possible to have an 
architecute that we might today consider "CISC" (for any number of reasons:
Reg-Mem instructions, 2 word instructions, fancier address modes, etc.) that
would be architected (I hate verbing nouns) to permit superscalar and out-of-
order execution, unlike current CISCs that gave no thought to the issues at
all (but I love run-on sentences).

This being the case, I believe that compiler technology can take advantage
of CISCy features, and that we'll see a resurgence of CISCs. But, they won't
be compatible with the ones we are familiar with.

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