🚀 go-pugleaf

In article <516@baird.cs.strath.ac.uk> jim@cs.strath.ac.uk writes:
>A RISC based multiprocessor machine would be an exciting prospect, but
>is likely to be difficult ...

Excuse me, but we seem to have done that some time back. A couple of
different models, even.... 8{)

>... it would need a *very* fast bus.

Yup. And it has one! Well, pretty fast anyway -- ~128 MB/sec. Alas, other
factors (like max backplane length, etc) tend to limit the number of processors
and otherwise constrain bus speeds, but it can be pushed up significantly
from that point. Or at least some variant could.

>Of course, fancy cacheing can reduce the demands on bus bandwidth, but
>that will make cache consistency harder 

And we have "fancy cacheing" and cache consistency. Of course, you don't 
*NEED* cache consistency when you build multiprocessors with cache, but
determinism is SUCH a nice feature....

Seriously, it's not too hard to do something like this. The real trick
is going to be supporting an arbitrarily large number of processors
with interconnections fast enough so as to make all memory appear to
be shared. Eugene Brooks' "KILLER MICROS" type scenario. Just imagine: 
a 64K-node hypercube with one's-of-nanoseconds message times....
Now THAT would be a seriously difficult to construct AND exciting
prospect....

Regards,

-- 
Stanley P. Hanks   Science Advisor                    Solbourne Computer, Inc.
Phone:             Corporate: (303) 772-3400           Houston: (713) 964-6705
E-mail:            ...!{boulder,sun,uunet}!stan!stan        stan@solbourne.com