Article View: comp.arch
Article #2981Re: Alliant/Intel PAX parallel computing standard
From: Stan Lackey
Date: Mon, 13 Nov 1989 16:14
Date: Mon, 13 Nov 1989 16:14
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1366 bytes
In article <36425@lll-winken.LLNL.GOV> brooks@maddog.llnl.gov (Eugene Brooks) writes: >In article <23184@cup.portal.com> mslater@cup.portal.com (Michael Z Slater) writes: >>Is anyone familiar with Alliant's loop-level parallelism scheme? >>Intel is pitching this as a major win for the i860, in that it gives them >>a binary standard for parallel computing, something no other processor has. >It may be a major "business win" for Intel, but the leading edge parallel >code writers using the Alliant are NOT using their loop-level parallelism >scheme. My take on this is that Intel may be considering only say a four processor system, where Alliant-style concurrency can work really well. It could be that Intel is thinking along the lines of a cache coherency scheme which only works on the bus-based model, which severely limits ther number of processors anyway. -Stan
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Path: arc1-ca.pugleaf.net!utzoo!utgpu!jarvis.csri.toronto.edu!mailrus!shadooby!samsung!usc!apple!bbn!bbn.com!slackey From: slackey@bbn.com (Stan Lackey) Newsgroups: comp.arch Subject: Re: Alliant/Intel PAX parallel computing standard Message-ID: <48124@bbn.COM> Date: 13 Nov 89 16:14:19 GMT References: <23184@cup.portal.com> <36425@lll-winken.LLNL.GOV> Sender: news@bbn.COM Reply-To: slackey@BBN.COM (Stan Lackey) Organization: Bolt Beranek and Newman Inc., Cambridge MA Lines: 16