Re: RISC multiprocessors

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Article #2982

#2982

From: James Shankland
Date: Mon, 13 Nov 1989 18:19

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In article <sZLhtay00UkaIj6al2@andrew.cmu.edu> bader+@andrew.cmu.edu (Miles Bader) writes:
>mslater@cup.portal.com (Michael Z Slater) writes:
>> Plus, the R3000 cache is write-through, and a reasonable
>> multiprocessor system needs write-back caches.
>
>Why?

Bus bandwidth limits.

(Hey, at least we're being economical with *net* bandwidth here :-)).

jas

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Path: arc1-ca.pugleaf.net!utzoo!utgpu!jarvis.csri.toronto.edu!mailrus!tut.cis.ohio-state.edu!ucbvax!pasteur!postgres!jas
From: jas@postgres.uucp (James Shankland)
Newsgroups: comp.arch
Subject: Re: RISC multiprocessors
Message-ID: <19505@pasteur.Berkeley.EDU>
Date: 13 Nov 89 18:19:22 GMT
References: <13319@pur-ee.UUCP> <280004@hpdml93.HP.COM> <23963@cup.portal.com> <sZLhtay00UkaIj6al2@andrew.cmu.edu>
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Reply-To: jas@postgres.berkeley.edu (Jim Shankland)
Organization: The Eddie Group
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