🚀 go-pugleaf

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>In article <255E15BB.12770@maccs.dcss.mcmaster.ca> cs4g6ag@maccs.dcss.mcmaster.ca (Stephen M. Dunn) writes:
>In article <36340@apple.Apple.COM> baum@apple.UUCP (Allen Baum) writes:
>$ What is the performance difference between a 32k cache  and a 31k cache?
>
>I have beside me an article stating that on the Berkeley RISC I and II chips,
>between 6 and 10 percent of the chip area was used for decoding and control
>logic.  Compare this with a figure of 50-60% on a 68000 or Z8000 ... now, I
>must admit that I've never designed an on-chip cache for a RISC chip, but
>somehow I think it would be quite easy to get more than a 1k cache out of
>40-54% of the chip size.  After all, if each 1k of cache size takes even 40%
>of the chip's area, how would you get a 32k (or, for that matter, 31k) cache
>on a chip in the first place?

It is not clear that the percentage of transistors used by control logic
is constant as the total number of transistors increases. That is, 50-60% of
the 68,000 transistors in a 68000 may have been control, but its a lot less
(percentage-wise) of the 250k (?) transistors of a 68030. By the time you 
start throwing large caches on board, the control percentage may be neglible,
even for a CISC. It was my contention that when you reach this point, the
cost of CISC control hardware is neglible, and the supposed superiority of
RISC (in this "area" {heh, heh} only!! :-)  is in serious question.


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