🚀 go-pugleaf

In article <31329@winchester.mips.COM> hawkes@mips.COM (John Hawkes) writes:
>In article <1358@bnr-rsc.UUCP> schow%BNR.CA.bitnet@relay.cs.net (Stanley T.H. Chow) writes:
>>
>>It seems to me the MIPS 55 MIPS (@ 60 MHz?) ECL system (chip set?)
>>is the "classical" approach for RISC designs to get higher through-
>>put. They do it by upping the clock-rate.
>>
>>Intel has gone the SuperScalar route. Their i960CA is said to be
>>66 MIPS @ 33 MHz. They have put the cleverness into multiple
>>execution units.
>
>Once again, let's not confuse apples and oranges.  Using the MIPS performance
>benchmark suite, the MIPS R6000-based *system* achieves 55 Vax-MIPS at 67-MHz.
>Since it's not a superscalar design, the system executes 67 million
>*instructions* at 67-MHz.  The ECL chipset is not the limiting factor at this
>clock rate.
>
>The i960 *chip* executes a theoretical max of 66 million *instructions* at
>33-MHz -- two per cycle.  I haven't heard Intel make any claims about how fast
>a Unix *system* would execute real applications.

Note that the above statement applies to the i960_CA_, whereas the quote below 
applies to the i960[KA,KB,MC,XA].  Also, note that at 67 MHz the R6000 can in
theory be executing two integer instructions (it still has the asynch mult/div
unit, no?) as well as I would guess two FP instructions.  However, it can only
ISSUE one instruction per cycle.  The 960 CA can issue three instructions per
cycle to the chosen three of four execute units.  I believe Intel has figures
showing that on the average they could infact issue two instructions per clock
_average_ [over what program set?], hence the 960CA can legitimately be called
66 Native MIPS average with 99 Native MIPS peak.  How this will work out in
"reality" who knows?  I'm looking forward to Specmarks for a 960CA Real
System!

>The Atlantic Research Corporation, an independent group, has done some
>comparisons between the MIPS R3000 (25-MHz) and a 20-MHz 80960 executing Ada
>programs (the "Common Avionics Processor Ada Benchmark Suite"), and they
>discovered that the R3000 was usually more than twice as fast on hand-coded
>programs, and overall was more than five times faster on compiled programs.
>
This comparison was to the 960_XA_, which was crippled by the register port
design needed to get the windows on the chip.  Steve McGeady posted here
a while ago on why Intel made the choices they did - the above comparison
says essentially nothing about how a 960CA, with relatively few register
file / bypass conflicts, would fare.  The JIAWG benchmarks are pretty 
silly anyway.
>John Hawkes
>{ames,decwrl}!mips!hawkes  OR  hawkes@mips.com