🚀 go-pugleaf

In article <1358@bnr-rsc.UUCP> schow%BNR.CA.bitnet@relay.cs.net (Stanley T.H. Chow) writes:
>
>It seems to me the MIPS 55 MIPS (@ 60 MHz?) ECL system (chip set?)
>is the "classical" approach for RISC designs to get higher through-
>put. They do it by upping the clock-rate.
>
>Intel has gone the SuperScalar route. Their i960CA is said to be
>66 MIPS @ 33 MHz. They have put the cleverness into multiple
>execution units.

Once again, let's not confuse apples and oranges.  Using the MIPS performance
benchmark suite, the MIPS R6000-based *system* achieves 55 Vax-MIPS at 67-MHz.
Since it's not a superscalar design, the system executes 67 million
*instructions* at 67-MHz.  The ECL chipset is not the limiting factor at this
clock rate.

The i960 *chip* executes a theoretical max of 66 million *instructions* at
33-MHz -- two per cycle.  I haven't heard Intel make any claims about how fast
a Unix *system* would execute real applications.

The Atlantic Research Corporation, an independent group, has done some
comparisons between the MIPS R3000 (25-MHz) and a 20-MHz 80960 executing Ada
programs (the "Common Avionics Processor Ada Benchmark Suite"), and they
discovered that the R3000 was usually more than twice as fast on hand-coded
programs, and overall was more than five times faster on compiled programs.

>Here is the $64,000 question:
>
>   Which part is easier to integrate into a real system? 

What kind of "real system"?  The R6000 is designed to be the heart of large,
general-purpose compute and/or file system server.  I don't think the same is
true of the i960.

-- 

John Hawkes
{ames,decwrl}!mips!hawkes  OR  hawkes@mips.com