🚀 go-pugleaf

In article <22303@gryphon.COM> scarter@gryphon.COM (Scott Carter) writes:

>ISSUE one instruction per cycle.  The 960 CA can issue three instructions per
>cycle to the chosen three of four execute units.  I believe Intel has figures
>showing that on the average they could infact issue two instructions per clock
>_average_ [over what program set?], hence the 960CA can legitimately be called
>66 Native MIPS average with 99 Native MIPS peak.  

I think that's too optimistic.
We've played some with an i860 on an evaluation board.
The supplied compilers didn't attempt to issue more than 
1 instruction/cycle (out of a max of three).  

On a simple matrix multiply (single precision fp), 

  multiplying 2 100x100 matrices took .52 seconds (3.8 MFlops)
  multiplying 2 400x400 matrices took 86 seconds  (1.5 MFlops)

versus a peak of 66 MFlops.  The poor performance on the larger
size shows the effect of the small on-chip data cache.

Using the VAST front-end, with hand coded vector primitives
gives about 8.5 MFlops.

Reworking by hand, being especially careful of the cache,
gives about 26.5 MFlops, for either size.
(This can be improved, but I think only slightly).
This is fairly hot, though still not 66 MFlops.

The challenge is getting compilers to take advantage of
tiny caches and long pipelines and multi-instruction issue,
as discovered below

>>discovered that the R3000 was usually more than twice as fast on hand-coded
>>programs, and overall was more than five times faster on compiled programs.

Sounds like the MIPS compilers are more mature.  Certainly it's an
easier target.

Preston Briggs