Article View: comp.arch
Article #3480Re: Dual FPUs?
From: Dan Hendrickson
Date: Fri, 16 Mar 1990 16:28
Date: Fri, 16 Mar 1990 16:28
13 lines
1065 bytes
1065 bytes
In article <24915@princeton.Princeton.EDU} haahr@princeton.edu (Paul Haahr) writes: }... the only applications (at least according to what people say }in this group) where the traditional supercomputers are significantly }faster than killer micros are vectorizable number crunchers. }.............................. For codes like these, wouldn't it be }possible to take advantage of two (or more) independent, off-the-shelf }floating point units? } I would venture to guess that 64 - 32 bit registers is insufficient to do much with in a vector machine. For instance, the Cray's have 8 - 64 x 64 bit vector registers, and I believe the users would like to see this number grow.
Technical Details
Message-ID:
<684@halley.UUCP>Path:
arc1-ca.pugleaf.net!utzoo!attcan!uunet!cs.utexas.edu!halley!danhReferences:
<24915@princeton.Princeton.EDU}Show Full Headers
Complete Article Headers
Path: arc1-ca.pugleaf.net!utzoo!attcan!uunet!cs.utexas.edu!halley!danh From: danh@halley.UUCP (Dan Hendrickson) Newsgroups: comp.arch Subject: Re: Dual FPUs? Message-ID: <684@halley.UUCP> Date: 16 Mar 90 16:28:48 GMT References: <24915@princeton.Princeton.EDU} Reply-To: danh@halley.UUCP (Dan Hendrickson) Distribution: comp Organization: Tandem Computers, Austin, TX Lines: 13