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Article #3481

Re: Indirect addressing on SIMD architectures

#3481
From: Joe Pfeiffer
Date: Fri, 16 Mar 1990 16:12
45 lines
2745 bytes
mshute@r4.uucp (Malcolm Shute), in <8332@hubcap.clemson.edu>:
|
|In article <8332@hubcap.clemson.edu> billo@nova.npac.syr.edu (Bill O) writes:
|>[about indirect addressing on SIMD]
|
|>      In terms of implementation, SIMD machines typically have bit
|>serial processors which are partitioned into small groups to share
|>memory chips and the like. Only one address is presented to each
|>memory chip, which produces a word full of data, which is then split
|>off into individual bits for each processor in the associated group.
|>Thus there is no opportunity for each processor to provide its
|>own address.
|
|Right, this is where I really question the value of this interpretation
|of Flynn's notation.
|
|What you have described seems to me to be a description of any SISD
|machine which can be implemented using bitslicing.  There's nothing
|wrong in that, of course.  My question to the net is, however, what is
|the value of the classification scheme if we can lump all bitwise-parallel
|von Neumann computers into the SIMD slot.
|
|Viewed the other way, if all of the processors access memory addresses
|in strict harmony like this, then they are only biting off parts of
|the *same* data stream.  (And hence all qualify as being SISD).
|Surely, it is only the MAMD machines which you mentioned later
|which can claim to qualify as true SIMD.

Of course, you're right.  This is similar to the reason that one of my
favorite questions at oral exams is ``argue that a single-CPU Cray-1
is an example of each of Flynn's categories.''

We generally interpret the bits making up a single word as a single
scalar value, making a von Neumann engine SISD instead of SIMD.  The
bits in a bit plane, however, we interpret as elements of a matrix, so
MPP is SIMD, not SISD.  This is also consistent with the common
placement of the scalars making up a matrix; each scalar is spread
across several planes within a single PE.

It is also possible to argue the MPP (for example) is MIMD, due to the
Mask bit; or even MISD because of asynchronous IO.  None of these are
particularly useful arguments to make, however, because ``SIMD'' best
captures the flavor of the machine.

-Joe.
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From: pfeiffer@nmsu.edu (Joe Pfeiffer)
Newsgroups: comp.arch
Subject: Re: Indirect addressing on SIMD architectures
Message-ID: <PFEIFFER.90Mar16091244@puye.nmsu.edu>
Date: 16 Mar 90 16:12:44 GMT
References: <8332@hubcap.clemson.edu> <1080@m1.cs.man.ac.uk>
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In-reply-to: mshute@r4.uucp's message of 14 Mar 90 16:52:42 GMT