🚀 go-pugleaf

In article <id.Z9WU.QA1@ferranti.com> peter@ferranti.com (peter da silva) writes:
>Of course, superscalar RISC machines with lots of pipelines are really terrible
>at handling byte-code interpreters (lots of non-predictable branches) and run-
>time code generation (OK, now we blow away the pipeline...). Oh, and the
>infamous autoincrement deferred addressing mode becomes a major win...

It ain't necessarily so.  You can use speculative or non-faulting
loads and multiple condition codes to pipeline the interpreter itself.
This is not a panacea, but it's not a catastrophe.  Not all RISCs have
these (yet).

It's also not clear to me that the stack machine will come with a
simpler pipeline.  Branches will probably be just as bad there, and
your autoincrement deferred addressing mode looks like a big consumer
of register file ports.  Superscalar group or messy addressing modes,
it's all the same in terms of hardware resources.

David Chase
Sun