🚀 go-pugleaf

> In article <38139@stellar.UUCP> wright@sol.UUCP () writes:
>Honeywells were basically IBM ripoffs with a special Gray-to-binary
>instruction added so they could work on radars on the DEW line.
>They had some interesting features; not only did they have an
>execute (XEC) instruction that would execute the instruction at the
>effective address, they had execute double (XED) that would execute
>the two instructions starting at the effective address.
>...

I have seen some discussion of the TMS-9900 microprocessor, but I don't
recall if it was here.  The 9900 has a similar instruction, X, whose
parameter is an effective address of the instruction to execute.  The
really wild thing is that, X R4, is valid because registers are in
memory.

BLWP is effectively a free context switch.  The 9900 has only three
hardware registers.  The status register, the PC, and the workspace
pointer, which is the address of the registers in memory.  When you
want to doodle with a piece of memory that is relatively small,
you can load the WP with the starting address and do you diddling.
Basically it goes something like

	MOV	@DIDDLE_AREA,R1
	MOV	@NEWCODE,R2
	BLWP	R1		R1 is effective address of descr
	JMP	AROUND
NEWCODE	EQU	$

	do some stuff using R0 though R12 for whatever purposes,
	maybe fast hardware memory mapped I/O.

	RTWP	Return to where we came from with old regs restored
AROUND	EQU	$
	continue doing something else

The other, maybe not so obvious, thing is that you can load object code into
registers and just call it or branch to it.

Given a larger address space than just 64K and a MMP, this architecture could
provide some unique opportunities for code size reduction.  Also, in C,
passing the address of a register variable would have meaning.

-- 
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gregg.g.wonderly@att.com   (AT&T bell laboratories)