🚀 go-pugleaf

In article <2610@phri.UUCP> roy@phri.UUCP (Roy Smith) writes:
>In article <985@rpics.RPI.EDU> yerazuws@rpics.RPI.EDU (Crah) writes:
>> A VAX has 32 bits- so if we assume (*) that all 32 can be used as memory
>> address, a VAX (or other 32-bit processor) can have AT MOST 4 GIG of memory.
>... Anybody willing to guess when we'll see 48 bit physical addresses on 32
> bit machines?  Anybody for demand paging and bank switching at the same time?

It's already happening.  The ROSETTA memory manager chip in the IBM PC RT
manages an address space that is 43 bits.  It manages 28-bit segments, of
which you can potentially have 32K.  (Actually, although the architecture
allows for 15 bit segment numbers, the current implementation limits you to
12, making your addresses 40 bits.)  The high 4 bits of a 32-bit address are
mapped to a 15 bit segment number using a fast 16-bit lookup which, now that
you mention it, is not unlike bank switching.  The current implementations of
the processor only support normal amounts of memory, e.g. 8MB, but you could
load it up  to a terabyte and user programs would only see fewer page faults.

The 370 XA architecture used in the 3090 series defines a funny kind of
memory for paging which is addressable in 4K chunks, and the only thing you
can do with it is to blat a chunk into or out of a 4K chunk of regular memory.
Think of that as a brute-force approach to bank switching given that they
couldn't build fast enough address decoders to switch banks the usual way.
-- 
John R. Levine, Javelin Software Corp., Cambridge MA +1 617 494 1400
{ ihnp4 | decvax | cbosgd | harvard | yale }!ima!johnl, Levine@YALE.something
Where is Richard Nixon now that we need him?