🚀 go-pugleaf

In article <2B51D662.29834@news.service.uci.edu> jtien@venice.eng.uci.edu  
(Joe Tien) writes:
> 
> Could someone direct me to a good definition of the harvard
> architecture? Is it dual memory port (each with own set of address and
> data bus) or is it just dual bus (separate address and data bus used for
> both instruction and data.)
> 
> If possible, I'd prefer some type of reference I can use in my paper,
> not that I don't trust the infinite wisdom of the net. :-)
> 
> Thanks,
> 
> Joe Tien
> jtien@balboa.eng.uci.edu

Basically the second!

Once it was called Zuse architecture (then von Neumann took over).
After a while it got a writable control/instruction (as you like it) store  
and was called Harvard architecture; just to take over in the modern DSP  
designs.

Just as a start for argument ;-)
-- 
Peter Nitezki       | Nitezki@NiDat.sub.org # Blessed thou who knoweth
Staarenbergstr. 44  | Tel.:  +49 7251 62495 # not about the pleasure and
D-7527 Kraichtal 2  | Fax :  +49 7251 69215 # delight of being hooked
GERMANY             |                       # up to the Net. Peter 1,3-5

In article <1993Jan24.180434.2420@nidat.sub.org>, Nitezki@NiDat.sub.org (Peter Nitezki) writes:

| Basically the second!
| 
| Once it was called Zuse architecture (then von Neumann took over).
| After a while it got a writable control/instruction (as you like it) store  
| and was called Harvard architecture; just to take over in the modern DSP  
| designs.

  I agree, and I don't have the refference, either.

  As a historical note, back in the bad old days I had an app which just
wouldn't fit in the 64k I could address with a Z80. And the budget
didn't allow something else (not that there was mush at that time). With
the help of a friend to hack the hardware, I came up with a solution, a
version of CP/M which loaded the program in one memory bank in so-called
"master mode," then jumped to the program in "slave mode."

  What we had done was bank switching, such that when the CPU did an
opcode fetch, the M1 cycle, it came from the code bank, and when the CPU
did any other data access it went in the "data" bank. The program was
all written in a B offshoot called IMP, so I could easily avoid the self
modifying code prevalent at that time.

-- 
bill davidsen, GE Corp. R&D Center; Box 8; Schenectady NY 12345
	A terible poker player can have a winning hand,
	A obnoxious fool can have a good idea.
	Both are winners, regardless of who has them.

Nitezki@NiDat.sub.org (Peter Nitezki) writes:

>In article <2B51D662.29834@news.service.uci.edu> jtien@venice.eng.uci.edu  
>(Joe Tien) writes:
>> 
>> Could someone direct me to a good definition of the harvard
>> architecture? Is it dual memory port (each with own set of address and
>> data bus) or is it just dual bus (separate address and data bus used for
>> both instruction and data.)
>> 
>> If possible, I'd prefer some type of reference I can use in my paper,
>> not that I don't trust the infinite wisdom of the net. :-)
>> 

>Basically the second!

>Once it was called Zuse architecture (then von Neumann took over).
>After a while it got a writable control/instruction (as you like it) store  
>and was called Harvard architecture; just to take over in the modern DSP  
>designs.

>Just as a start for argument ;-)


My understanding is that a Harvard architecture consists of two _seperate_
buses, one for data and one for instructions.  I have no references at
hand.  But, Motorola used the term in their lititure describing the internal
buses on the 030 or 040.
--
^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
Emil Rojas  emil@shell.portal.com (408) 973-0603
Cognisys Software Systems Development
San Jose, CA 95129