Cache design for VLIW arch.

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1 total messages Started by Han Kyung Nam Thu, 10 Oct 1996 00:00

#23004

Author: Han Kyung Nam
Date: Thu, 10 Oct 1996 00:00

15 lines
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like superscalar, VLIW can execute more instructions in one cycle.
but, if external instruction bus width is 32 bits (= 1 instruction width),
then I think there will be so many miss penalties than uni-processor's when
cache miss occurs.
so, how can I solve this problem for better optimized performance?

And,
I've heard there are many processors using VLIW arch in the world,
one example is 
Philips' TriMedia DSP chip that uses 16K VLIW instruction cache.
but it's not easy to find papers or books that mentions this cache.
can you help me find these things?

Thank you...

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