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As an alternative to implementing logarithmic companding digitally,
I am intersted in investigating the possibility of performing any
processing of log companded signals without conversion. In particular
whether there are any techniques for combining (ie summing) signals
in the log domain. Once again, if anyone has any pointers to any
work in this area it would be much appreciated.

Thanks,

Mark
------------------------------------------------+-----------------------------+
Mark Summerfield, Telecom Research Laboratories | "A witty saying proves      |
ACSnet[AARN/Internet]: m.summerfield@trl.oz[.au]|       nothing." -- Voltaire |
Snail: PO Box 249, Clayton, Vic., 3168          +-----------------------------+

In article <1991Mar8.052136.11121@trl.oz.au> m.summerfield@trl.oz.au writes:
>I am currently investigating implementation of A-law and u-law (that's
>mu-law :-) companding techniques. I am aware of the formulae which are
>used to generate these, however I am more interested in practical fast
>software and digital hardware implementations, in which the calculation
>of logarithms is impractical.

No one computes logarithms to do u-law or a-law companding.  Decompression
is easy to accomplish with a lookup table: only 256 entries are required.
You can go the other way in only a small number of instructions; I suggest
checking out the handbook for any DSP chip; all that I've seen include
fast algorithms for u-law and a-law compresion and expansion.

>on the subject, I was wondering if anyone out there can point me in the 
>direction of any examples of previous work in this area. I would be
>particularly interested in any examples of custom (VLSI) implementations.

There's really a very small amount of computation required; it would be
easy to do in hardware.

--
--
Joe Buck
jbuck@galileo.berkeley.edu	 {uunet,ucbvax}!galileo.berkeley.edu!jbuck	

In article <11858@pasteur.Berkeley.EDU> jbuck@galileo.berkeley.edu.UUCP (Joe Buck) writes:
>In article <1991Mar8.052136.11121@trl.oz.au> m.summerfield@trl.oz.au writes:
>>I am currently investigating implementation of A-law and u-law (that's
>>mu-law :-) companding techniques. I am aware of the formulae which are
>>used to generate these, however I am more interested in practical fast
>>software and digital hardware implementations, in which the calculation
>>of logarithms is impractical.
>>on the subject, I was wondering if anyone out there can point me in the 
>>direction of any examples of previous work in this area. I would be
>>particularly interested in any examples of custom (VLSI) implementations.

The Motorola 56116/56156 SSIs implement the A/MU law compression
/decompression as an option. The necessary logic was designed in
and it is transparent to the user; all you need to do is to 
select a mode bit. the implementation is proprietary.

The laws, A/Mu, are linear by segment, and by studying 
the CCITT specification (Rec G711; Fascicle III.3 pp 68-71)
you can figure out the necessary logic.

You can also get the Motorola app. note on the 56000/1
compression/expension; the CCITT tables are reproduced.

Eric Cheval
Motorola DSP Group
Austin TX.

I signed my rights away for a design that I did for the telcom company
I used to work for that did u-law/a-law companding (and addition for
conferencing) in a TDM nonblocking switch for military and air traffic
applications.  It was done in pure synchronous hardware and they have
a patent application in for the whole system.  They are implementing
it in an ASIC right now.  I have to look at the legal agreement that
I signed, but I'd be willing to discuss general ideas if the original
poster has a noncommercial application in mind (I don't have the
original post).