DSP56001 timing query

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1 total messages Started by Mark James Tue, 17 Oct 1989 00:40

#461

Author: Mark James
Date: Tue, 17 Oct 1989 00:40

10 lines
646 bytes

Is it guaranteed that external memory accesses by the
DSP56001 will be separated by a whole number of instruction
cycles (i.e. 0,1,2..) when running with zero wait states
or is it possible that the gap could be 1/2, 1 1/2, 2 1/2, ...
cycles.

Thank you.

Mark James
mrj@basser.cs.su.oz

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