Article View: comp.lang.verilog
Article #113`timescale
From: Ralph Valentino
Date: Wed, 14 Oct 1992 21:45
Date: Wed, 14 Oct 1992 21:45
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If I use `timescale at all in a verilog file, the tf_gettime() call seems to die (always returns 0 even after simulation time passes). Has anyone seen similar effects or have an alternate method of accessing simulation time? I'm using verilog 1.6b-beta, but I've witnessed this in earlier revs as well. Unfortunately, my most recent copy of the PLI reference manual is 1.5a - it doesn't seem to help. Wild and crazy ideas accepted, -Ralph =============== Ralph Valentino (ralf@chpc.org) (ralf@wpi.wpi.edu) Hardware Engineer, Worcester Polytechnic Institute Center for High Performance Computing, Marlborough MA
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Path: arc1-ca.pugleaf.net!sparky!uunet!kithrup!hoptoad!pacbell.com!ames!sun-barr!olivea!charnel!rat!usc!news.bbn.com!noc.near.net!chpc.chpc.org!ralf From: ralf@chpc.org (Ralph Valentino) Newsgroups: comp.lang.verilog Subject: `timescale Keywords: PLI Message-ID: <1992Oct14.214521.27680@chpc.org> Date: 14 Oct 92 21:45:21 GMT Organization: Center For High Performance Computing Lines: 15