🚀 go-pugleaf

Re: __Cut and Paste C codes, you can have your hardware!
By: Jonathan Bromley on Mon, 12 Mar 2001 17:23

__Cut and Paste C codes, you can have your hardware!
By: kctang on Mon, 12 Mar 2001 07:13

Qualis Top-Down Design With Verilog Course: July 17-21
By: Clifford E. Cummings on Thu, 15 Jun 1995 00:00

COURSE: High Level Design Using VHDL, Oct 30-Nov 3, Beaverton OR
By: training on Fri, 06 Oct 1995 00:00

COURSE: High Level Design Using Verilog, Nov 6-10, Beaverton OR
By: training on Fri, 06 Oct 1995 00:00

COURSE: High Level Design Using Verilog, Oct 9-13, Beaverton OR
By: training on Fri, 15 Sep 1995 00:00

COURSE: High Level Design Using VHDL, Oct 2-6, Beaverton OR
By: training on Fri, 15 Sep 1995 00:00

COURSE: High Level Design Using Verilog, Dec, Jan, Feb, Beaverton OR
By: Qualis Training Registrar on Fri, 01 Dec 1995 00:00

COURSE: High Level Design Using VHDL, Feb, Beaverton OR
By: Qualis Training Registrar on Fri, 01 Dec 1995 00:00

COURSE: High Level Design Using VHDL, Dec, Feb, Beaverton OR
By: Qualis Training Registrar on Thu, 23 Nov 1995 00:00

COURSE: High Level Design Using Verilog, Dec, Jan, Feb, Beaverton OR
By: Qualis Training Registrar on Thu, 23 Nov 1995 00:00

COURSE: Advanced Techniques Using Verilog, March 4-6, Beaverton OR
By: Training Registrar on Wed, 31 Jan 1996 00:00

COURSE: High Level Design Using Verilog, Feb 12-16, Beaverton OR
By: Training Registrar on Wed, 31 Jan 1996 00:00

COURSE: High Level Design Using VHDL, March 11-15, Beaverton OR
By: Qualis Registrar on Wed, 31 Jan 1996 00:00

COURSE: High Level Design Using Verilog, March 25-29, Beaverton OR
By: Qualis Training Registrar on Tue, 27 Feb 1996 00:00

COURSE: High Level Design Using VHDL, March 11-15, Beaverton OR
By: Qualis Training Registrar on Tue, 27 Feb 1996 00:00

COURSE: Advanced Techniques Using Verilog, March 18-20, Beaverton OR
By: Qualis Training Registrar on Tue, 27 Feb 1996 00:00

ANNOUNCE -- TRAINING: Intro/Advanced High Level Design Using HDLs, Bay Area
By: Qualis Training Registrar on Wed, 03 Apr 1996 00:00

COURSES: Intro/Advanced High Level Design Using HDLs, Santa Clara, CA
By: Qualis Training Registrar on Mon, 18 Mar 1996 00:00

JOB: USA-CA-San Jose: EDA Applications Engineer
By: Rich Newton on Wed, 28 Apr 1999 00:00

Job Opening - Corporate Applications Engineer
By: Viewlogic Systems, Inc. on Thu, 09 Feb 1995 15:38

Wanted talented design/verification engineers for the Indus family.
By: Samir Palnitkar on Tue, 02 Jan 1996 00:00

VERIFICATION ENGINEER OPENING
By: Daniel Chapiro on Mon, 06 Jan 1997 00:00

Looking for ASIC layout contractor with Cadence tool experience
By: Michael T. Horne on Thu, 28 Aug 1997 00:00

Re: Verilog Won & VHDL Lost? -- You Be The Judge!
By: Michelle Anne Steiner on Fri, 12 May 1995 00:00

SW Engineer: San Jose, C/C++, EDA, Flex/Bison, Verilog/VHDL
By: Rich Edelman on Fri, 25 Oct 1996 00:00

Premodded Video Games & Backups For Sale
By: milli on Thu, 11 Jun 2009 01:20

Re: Verilog <--> VHDL translators
By: Masaharu Goto on Mon, 11 Jan 1993 17:50

Re: Verilog <--> VHDL translators
By: John Cooley on Tue, 05 Jan 1993 05:46

Verilog books
By: Andrew Guillaume on Fri, 29 Jan 1993 04:53

Books on Verilog
By: Jim Hunt on Wed, 27 Jan 1993 03:49

Best possible Verilog Reference: Also software Harddware co-design
By: Tapas Shome on Wed, 27 Jan 1993 06:22

Int'l Conference on CAD, ICCAD93 (CFP: papers due 4/12/93)
By: Gaetano Borriello on Tue, 26 Jan 1993 17:04

Re: Verilog code for Inverted, Open collector
By: Chandresh Patel on Fri, 22 Jan 1993 21:43

Free Xilinx Simulation Interface for Verilog
By: Daniel R. Kegel on Fri, 22 Jan 1993 18:48

Joining ESNUG
By: John Cooley on Thu, 21 Jan 1993 05:44

Request for information on a verilog mode for GNU Emacs
By: Roy Tobin on Thu, 21 Jan 1993 18:13

Re: Verilog code for Inverted, Open collector, Output Enable Bus
By: Clifford E Cummings on Thu, 21 Jan 1993 20:53

Verilog code for Inverted, Open collector, Output Enable Bus
By: Tai Phan on Thu, 21 Jan 1993 16:17

Re: execution of always blocks
By: Leonardo LAGOS M on Sat, 19 Dec 1992 12:43

Re: execution of always blocks
By: Clifford E Cummings on Fri, 18 Dec 1992 23:57

Re: execution of always blocks
By: Steve Ehlers on Fri, 18 Dec 1992 20:01

Re: execution of always blocks
By: Rajesh Patil on Fri, 18 Dec 1992 17:44

Re: execution of always blocks
By: Alan Bair on Fri, 18 Dec 1992 09:07

Conversion of Verilog timing checks to VHDL?
By: Daniel R. Kegel on Fri, 18 Dec 1992 04:36

execution of always blocks
By: Terry Manley on Thu, 17 Dec 1992 07:15

Verilog <--> VHDL translators
By: Tony Pham on Fri, 18 Dec 1992 02:46

Ignore this dumb test message!
By: gordjericho.uucp Gord Wait on Tue, 15 Dec 1992 18:55

Re: verilog and synthesis
By: John Cooley on Sun, 13 Dec 1992 04:08

Re: HELP:Verilog to VHDL translator
By: Interpretive Systems on Mon, 23 Nov 1992 23:14

Does OVI read mail?
By: Richard D. Schlotfeldt on Mon, 23 Nov 1992 22:37

Re: Wanted: VHDL to Verilog Translator
By: George Haber on Mon, 23 Nov 1992 20:20

2nd Annual Int'l Verilog HDL Conference - March 22-24
By: OVI on Mon, 23 Nov 1992 19:31

HELP:Verilog to VHDL translator
By: Masaharu Goto on Thu, 19 Nov 1992 16:34

Verilog LSI/MSI libs?
By: Manolis Stratakis on Fri, 20 Nov 1992 10:40

Re: 3rd Party Verilog Compilers
By: My name is... on Fri, 20 Nov 1992 01:33

Info about OVI and status of Verilog
By: Clint Olsen on Fri, 20 Nov 1992 00:22

Memory Addressing in verilog
By: Elliot H. Mednick on Thu, 19 Nov 1992 15:44

Re: Avoiding inertial delay in delay lines
By: Cindy Eisner on Wed, 18 Nov 1992 06:16

Memory Addressing in verilog
By: Steve Wood on Wed, 18 Nov 1992 18:19

Re: emacs verilog mode
By: Bruce Dunlop on Wed, 18 Nov 1992 02:45

Invite to Join ESNUG
By: John Cooley on Wed, 18 Nov 1992 09:20

Re: Does Cadence still exist?
By: Scott Johnson on Tue, 17 Nov 1992 10:32

Re: 3rd Party Verilog Compilers
By: Tom Anderson on Tue, 17 Nov 1992 03:27

Re: 3rd Party Verilog Compilers
By: Larry Augustin on Tue, 17 Nov 1992 00:19

Re: 3rd Party Verilog Compilers
By: Jeff West on Mon, 16 Nov 1992 19:28

Contacting Verilog
By: Pat Brans on Mon, 16 Nov 1992 17:27

Re: Avoiding inertial delay in delay lines
By: Steven Leung on Mon, 16 Nov 1992 16:38

Does Cadence still exist?
By: Ken Hornstein on Mon, 16 Nov 1992 05:34

Re: Avoiding inertial delay in delay lines
By: Steve M. Burinsky on Mon, 16 Nov 1992 04:52

Re: Verilog <--> VHDL translators
By: Masaharu Goto on Tue, 22 Dec 1992 23:46

Re: Verilog <--> VHDL translators
By: George Lippincott on Tue, 22 Dec 1992 23:42

Re: New question - lint like verilog checker
By: Interpretive Systems on Tue, 22 Dec 1992 22:40

Re: Verilog Syntax/Semantics Checker
By: Dan Sharoni on Tue, 22 Dec 1992 17:37

Re: New question - lint like verilog checker
By: Jeff West on Tue, 22 Dec 1992 15:53

Re: Verilog <--> VHDL translators
By: Masaharu Goto on Mon, 21 Dec 1992 18:07

New question - lint like verilog checker
By: Terry Manley on Tue, 22 Dec 1992 00:17

Summary : execution of always blocks
By: Terry Manley on Mon, 21 Dec 1992 23:57

Re: execution of always blocks
By: Michael Lodman on Tue, 22 Dec 1992 02:11

Re: Does verilint exist?
By: George Haber on Fri, 16 Oct 1992 17:18

Re: Help!! regarding gate delays!!!!
By: Seetamraju on Fri, 16 Oct 1992 22:23

Help!! regarding gate delays!!!!
By: Albatross on Fri, 16 Oct 1992 18:53

Verilog help required.
By: Gary Cook on Fri, 16 Oct 1992 12:58

Verilog mode for emacs?
By: Jeff Carlson on Thu, 15 Oct 1992 14:35

`timescale
By: Ralph Valentino on Wed, 14 Oct 1992 21:45

Re: Does verilint exist?
By: David Banks on Wed, 14 Oct 1992 17:25

Verilog mode for emacs?
By: Jeff Carlson on Wed, 14 Oct 1992 19:57

Deadline Extended--Call for Papers, Int'l Verilog HDL Conf.
By: OVI on Wed, 14 Oct 1992 17:45

Looking for Verilog Success Stories
By: OVI on Wed, 14 Oct 1992 18:30

Re: Accessing command line arguments
By: W. Scott Cranston on Wed, 30 Sep 1992 02:34

Re: emacs verilog-mode bug report
By: Richard Eversole; x6239 on Mon, 12 Oct 1992 13:22

Implicit type conversion
By: Ken Hanson on Tue, 13 Oct 1992 16:34

Re: Does verilint exist?
By: hendrix on Mon, 12 Oct 1992 18:02

Concantenation Problems
By: Elliot H. Mednick on Sat, 10 Oct 1992 15:03

Concantenation Problems
By: Belliappa Kuttanna on Fri, 09 Oct 1992 18:52

Does verilint exist?
By: Mark Sprague on Fri, 09 Oct 1992 20:56

Help with VerilogIn please
By: dan schumacher on Fri, 09 Oct 1992 20:45

Concantenation Problems
By: Belliappa Kuttanna on Fri, 09 Oct 1992 18:48

Re: Variable width assignments?
By: W. Scott Cranston on Sat, 26 Sep 1992 23:09

Re: legality of force? (answer)
By: Charles Robert Yount on Wed, 07 Oct 1992 20:03

Re: Avoiding inertial delay in delay lines
By: Rajesh Patil on Fri, 13 Nov 1992 18:28

Wanted: Informations on parallel VHDL/Verilog Simulators
By: Finnegan T. Tsai on Thu, 12 Nov 1992 19:58

3rd Party Verilog Compilers
By: Bruce Dunlop on Thu, 12 Nov 1992 21:11

Wanted: Informations on parallel VHDL/Verilog Simulators
By: Finnegan T. Tsai on Thu, 12 Nov 1992 23:41

Re: Avoiding inertial delay in delay lines
By: Steven Leung on Thu, 12 Nov 1992 16:31

Re: Avoiding inertial delay in delay lines
By: Eric Hughes on Thu, 12 Nov 1992 14:26

Avoiding inertial delay in delay lines
By: Steve M. Burinsky on Thu, 12 Nov 1992 05:33

Verilog lex/yacc grammar
By: Dennis Allison on Thu, 05 Nov 1992 16:45

Tasks & Libraries
By: Jens-Uwe Dzikowski on Thu, 05 Nov 1992 15:28

Call for Papers Deadline Extension - Int'l Verilog HDL Conference
By: OVI on Tue, 06 Oct 1992 20:09

Public Domain Verilog perser/compiler
By: Marek Ryniejski; x6259 on Wed, 23 Sep 1992 10:24

Re: Verilog products for the PC
By: A Johnstone on Fri, 02 Oct 1992 13:30

legality of force?
By: Charles Robert Yount on Fri, 02 Oct 1992 20:45

Re: Verilog products for the PC
By: Nelson Willhite on Wed, 30 Sep 1992 19:28

Verilog products for the PC
By: Ken Hanson on Tue, 29 Sep 1992 15:59

Verilog-HDL Mode for emacs
By: Lech Slawomir Tomczak on Tue, 29 Sep 1992 10:15

Coding for Synopsys
By: John Waite on Mon, 28 Sep 1992 20:30

Re: Variable width assignments?
By: Cindy Eisner on Sun, 27 Sep 1992 06:23

Variable width assignments?
By: Elliot H. Mednick on Sun, 27 Sep 1992 01:03

ESNUG goes on Vacation!
By: John Cooley on Fri, 04 Sep 1992 15:44

Analogue modeling by Verilog
By: Fung Ka Hing on Thu, 03 Sep 1992 07:15

Re: Verilog models for 74xxx?
By: Richard Eversole; x6239 on Tue, 01 Sep 1992 10:38

Re: readmem
By: Richard Eversole; x6239 on Mon, 31 Aug 1992 13:35

Verilog models for M68000 M68020 M68030 etc.
By: hitesh on Tue, 01 Sep 1992 18:45

Re: NDL to Verilog translator
By: K. Parthiban on Tue, 01 Sep 1992 00:51

Incremental Pattern File tasks
By: Khaldoun Alzien on Mon, 31 Aug 1992 21:20

Re: NDL => Verilog Translator
By: Julian Fields on Sat, 29 Aug 1992 00:13

Verilog models for 74xxx?
By: Jonathan D. Hampton on Thu, 27 Aug 1992 15:01