🚀 go-pugleaf

Greetings,

If anyone knows a simple way to describe in Verilog an Open collector, Inverted,
with Output enable bus, please help.  The parameters are as follow:

// Verilog code

input [31:0] inp;               // Input bus
input oen_;                     // Output enable
output [31:0] outp_;            // Output bus

// When oen_ is 1, outp_ should be 32'hzzzzzzzz
// when oen_ is 0, outp_ is 0 if inp is 1, and z if inp is 0 (OC inverted)
// For single bit, I have the code that works:

wire [31:0] outp_;
assign outp_[31] = (~oen_ && inp[31]) ? 'b0 : 'bz;
assign outp_[30] = (~oen_ && inp[30]) ? 'b0 : 'bz;
.......
and so on
But this takes a lot of space, and typing. I want to use one or two lines
to describe the entire 32 bits bus.

Thanks,

Tai Phan
--------
Interphase Corp.
(214) 919 9000
phan@iphase.com


-- 
Tai Phan  X218
phan@iphase.com