Article View: comp.lang.verilog
Article #158Re: execution of always blocks
From: Leonardo LAGOS M
Date: Sat, 19 Dec 1992 12:43
Date: Sat, 19 Dec 1992 12:43
51 lines
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2107 bytes
Alan Bair (abair@parsons.sps.mot.com) wrote:
: In article <13665@optilink.COM> manley@optilink.COM (Terry Manley) writes:
:> More specifically why doesn't the following work:
:>
:> reg a,b,c;
:>
:> always @(posedge Clk) c = b;
:> always @(posedge Clk) b = a;
:>
:> always @(posedge Clk)
:> fork
:> c = b;
:> b = a;
:> join
:>
: However, this has the same problem as the two always blocks, there is no
: control over which will take place first. I can't remember the exact syntax,
: but there is a way to specify that the values of b & a are first saved and
: then the assignments take place. This allows them to occur in any order, but
: get the results you are after.
:
What you want to do is something like this :
always @(posedge Clk) c <= #1 b;
always @(posedge Clk) b <= #1 a;
This code means " evaluate b at posedge of Clk, save this value, and assign
it to c 1 time later."
This syntax is also called "non-blocking assignment" (or similar).
Idem for the second always.
:> --
:> dave
:> manley@optilink.com
:>
: --
: Alan Bair AMCU DSCS
: Motorola, Inc. (Design Software &
: Mail Stop OE-320 Computer Services)
: 6501 William Cannon Dr. West
: Austin, TX 78735-8598 abair@parsons.sps.mot.com
Hope this can help you,
Leo
--
. e-mail : llagos@renoir.die.udec.cl
|\ | / cc : llagos@halcon.dpi.udec.cl
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Newsgroups: comp.lang.verilog Path: arc1-ca.pugleaf.net!sparky!uunet!uchdcc!uconce!renoir!llagos From: llagos@renoir.die.udec.cl (Leonardo LAGOS M) Subject: Re: execution of always blocks Sender: usenet@halcon.dpi.udec.cl Message-ID: <Dec19.124345.50968@halcon.dpi.udec.cl> Date: Sat, 19 Dec 92 12:43:45 GMT References: <ABAIR.92Dec18020726@parsons.sps.mot.com> Organization: Universidad de Concepcion, Concepcion - Chile X-Newsreader: TIN [version 1.1 PL7] Lines: 51