🚀 go-pugleaf

In article <1992Dec18.200153.25828@twisto.eng.hou.compaq.com> ehlers@tiktok.eng.hou.compaq.com (Steve Ehlers) writes:
>In article <1992Dec18.174451.11544@newsgate.sps.mot.com> rajesh@chdasic.sps.mot.com writes:
>>manley@optilink.COM (Terry Manley) writes:
>>
>>> always @(posedge Clk) c = b;
>>> always @(posedge Clk) b = a;
>>
>>If you have to use two always blocks, you could put
>>a #0 delay before the procedural assignment that you want
>>done last. That will make VerilogXL schedule that event
>>for processing at the end of that timestamp.
>
>Which is fine if you only care about which ONE is last.  If you have 
>three (or more) registers, you'll still have problems.  Using the
>non-blocking assignment operator ( <= ) will give you the behavior you want:
>
> always @(posedge Clk) c <= b;
> always @(posedge Clk) b <= a;

Intra-assignment timing provides another alternative
(The following example can be run as is).

/* Example of "intra-assignment" timing control across */
/* procedural blocks. Placing timing control on the    */
/* right-hand side (RHS) of the "=" causes temporary   */
/* storage of the RHS variable, and schedules future   */
/* assignment using the stored RHS value.              */
/*                                                     */
/* Cliff Cummings - 12/18/92                           */

`timescale 1ns /100ps
module Qintra;
  reg [3:0] a, b;
  reg clk;

  // Wait 1 time unit to allow initial assignment of "b"
  always #1 a = @(posedge clk) b;

  // Wait 1 time unit to allow initial assignment of "a"
  always #1 b = @(posedge clk) a;

  initial begin
      clk = 0;
      forever #10 clk = ~clk;
    end

  initial begin
      $timeformat(-9, 2, "ns", 10);
      #1 $monitor($time, ": a = %h,  b = %h", a, b);
    end

  initial begin
      a=4'h5; b=4'ha;
      #100 $stop;
      #100 $finish;
    end
      
endmodule