🚀 go-pugleaf

In article <1992Dec18.174451.11544@newsgate.sps.mot.com> rajesh@chdasic.sps.mot.com writes:
>manley@optilink.COM (Terry Manley) writes:
>
>> always @(posedge Clk) c = b;
>> always @(posedge Clk) b = a;
>
>If you have to use two always blocks, you could put
>a #0 delay before the procedural assignment that you want
>done last. That will make VerilogXL schedule that event
>for processing at the end of that timestamp.

Which is fine if you only care about which ONE is last.  If you have 
three (or more) registers, you'll still have problems.  Using the
non-blocking assignment operator ( <= ) will give you the behavior you want:

 always @(posedge Clk) c <= b;
 always @(posedge Clk) b <= a;