🚀 go-pugleaf

manley@optilink.COM (Terry Manley) writes:

> always @(posedge Clk) c = b;
> always @(posedge Clk) b = a;

Verilog does not guarantee the sequence of execution of
multiple procedural blocks such as the always blocks above.
If you have to use two always blocks, you could put
a #0 delay before the procedural assignment that you want
done last. That will make VerilogXL schedule that event
for processing at the end of that timestamp.

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Rajesh Patil
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Advanced Product Operations                 rajesh@chdasic.sps.mot.com
Motorola ASIC                               
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