🚀 go-pugleaf

In article <rfall-240992171955@andrich.mv.us.adobe.com>rfall@mv.us.adobe.com (Richard Fall) 
writes:
> 
> Does anyone know if there's an easy way of doing the following
> in Verilog?
> 
>     I would like to be able assign a fixed value (say, zero),
>     declared as a single parameter ("zero") in assignment
>     statements where the variable on the LHS of the statements
>     may be of different bit width.
>     
>     That is, if I have the following:
>     
>         reg [1:0] foo;
>         reg [2:0] foolong;
>         
>     I would like to be able to say:
>      
>          foo = zero;
>          foolong = zero;
>          
>     and have the correct assignment take place.
>      
>     
>     Before you rush to tell me that Verilog already does that
> by zero-extending the RHS side to fit the LHS side, I'll point
> out that I may want to do the same thing with a parameter in
> which zero-extending is not the correct behavior.  For
> example, I may want the value "5555...." to be assigned to
> registers that may be any multiple of 4 bits wide.
> 
>     If there were a "sizeof" operator, this would be easy
> to do by using it in conjunction with repeated concatenation
> to produce the desired effect, but no such operator appears to
> exist.
> 
>     Am I missing something, or is there a clever way to do this?
> 
> 

You could make a max length integer which consists of the specified
integer repeated and assign it to the LHS.  Verilog will truncate to
the correct size.  For instance:

	reg [3:0] foo;
	reg [15:0] foolong;

	parameter rhs = (1E6{4'h5}};
	foo = rhs;
	foolong =  rhs;



foo will be 4'h5 and foolong will be 16'h5555.


Of course, 1E6 is too big, but use whatever you need.

Good Luck,
  Scott Cranston
  Cadence Design Systems




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