Article View: comp.lang.verilog
Article #73Re: NDL to Verilog translator
From: K. Parthiban
Date: Tue, 01 Sep 1992 00:51
Date: Tue, 01 Sep 1992 00:51
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Apropos the query for an NDL to Verilog translator, I presume you are looking for a gate level netlist translator. Perhaps you know this already or perhaps this is irrelevant. FWIW, do you have access to Synopsys? If so, you could read in Verilog and output NDL or vice-versa! ciao K.Parthiban
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Path: arc1-ca.pugleaf.net!sparky!uunet!olivea!decwrl!pa.dec.com!engage.pko.dec.com!e2big.mko.dec.com!asic.dec.com!kandappan From: kandappan@asic.dec.com (K. Parthiban) Newsgroups: comp.lang.verilog Subject: Re: NDL to Verilog translator Message-ID: <1992Aug31.215423.16847@e2big.mko.dec.com> Date: 1 Sep 92 00:51:12 GMT Sender: guest@e2big.mko.dec.com (Guest (DECnet)) Organization: Digital Equipment Corporation Lines: 9