🚀 go-pugleaf

Ok, I've got a 'newbie' question.

What's the story with this language?

More specifically why doesn't the following work:

reg a,b,c;

always @(posedge Clk) c = b;
always @(posedge Clk) b = a;

When the following does:

always @(posedge Clk)
  begin
	c = b;
	b = a;
  end

In the first case for some reason verilog may perform the "b = a"
assignment first, thereby throwing away the expected value that c was
going to get.  We've even seen cases where in a given simulation
sometimes it works correctly, sometimes it doesn't.

Ideally one would want the data transfer at the posedge of the clock
to behave like digital logic, that is it would, in this case behave
like a shift register.  Instead we get what looks like a shift
register with a bad hold time problem. 

So what is the story with multiple always blocks?
Is this something to worry about between modules?
How about between modules in different files?


--
dave
manley@optilink.com