Article View: comp.lang.verilog
Article #151Verilog <--> VHDL translators
From: Tony Pham
Date: Fri, 18 Dec 1992 02:46
Date: Fri, 18 Dec 1992 02:46
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Does anyone know of any good verilog to vhdl or vhdl to verilog translators? It would be quite helpful for my school work at this point. Any available public domain tools would be a big plus since my budget is limited. Appreciate any replies. Thanks.
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Newsgroups: comp.lang.verilog Path: arc1-ca.pugleaf.net!sparky!uunet!spool.mu.edu!caen!tpham From: tpham@engin.umich.edu (Tony Pham) Subject: Verilog <--> VHDL translators Message-ID: <d+V=MG#@engin.umich.edu> Date: Thu, 17 Dec 92 21:46:18 EST Organization: University of Michigan Engineering, Ann Arbor Distribution: usa Nntp-Posting-Host: engine.engin.umich.edu Lines: 5