Conversion of Verilog timing checks to VHDL?

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Article #153

#153

From: Daniel R. Kegel
Date: Fri, 18 Dec 1992 04:36

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Hi all,
is there an accepted idiom for expressing the sort of timing checks
supported in Verilog, i.e.
    $width(negedge x, t0);
    $setup(x, posedge y, t0);
    $hold(posedge x, y, t0);
in VHDL?

I'm thinking about converting a PD program that generates Verilog
to also generate VHDL.
- Dan Kegel (dank@blacks.jpl.nasa.gov)

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Newsgroups: comp.lang.verilog,comp.lang.vhdl
Path: arc1-ca.pugleaf.net!sparky!uunet!elroy.jpl.nasa.gov!dank
From: dank@blacks.jpl.nasa.gov (Daniel R. Kegel)
Subject: Conversion of Verilog timing checks to VHDL?
Message-ID: <dank.724653378@blacks.jpl.nasa.gov>
Sender: news@elroy.jpl.nasa.gov (Usenet)
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Organization: Image Analysis Systems Group, JPL
Date: Fri, 18 Dec 1992 04:36:18 GMT
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