🚀 go-pugleaf

As part of the Standard Release of Verilog from Cadence you should
be able to find a directory called examples/libraries.
Here you will find two important files:

   CDS_GEN_LIBS.v  and CDS_GEN_UDPS.v

These two files contain the "generic" library that Cadence uses as
the basis for all the models it produces. While this library will not
show you how to select the timing for devices you know it does show 
you the way to model various devices typically found in an ASIC
library. 

These same files should be present in the release for the version
of Verilog integrated with Design Framework II.

Cadence has been shipping these example models since it's 1.6 release.

Additionally, Cadence does provide(at a charge of course) a library of
standard "TTL", "CMOS" and "ECL" parts for use in board and system 
level design. These models are Verilog HDL and provide a good source
of how to model these types of devices.

-- 
  
  =====================================================================

    eversole@cadence.com
  
    Live long and prosper !

    |Standard disclaimers apply: I speak for myself and not Cadence|