Analogue modeling by Verilog

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Article #77

#77

From: Fung Ka Hing
Date: Thu, 03 Sep 1992 07:15

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I am a new learner of verilog.  I want to find some information about the
ability of modelling analog circuit by verilog.  

Would someone help me please?

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Message-ID: <1992Sep3.071552.9412@uxmail.ust.hk>

Path: arc1-ca.pugleaf.net!sparky!uunet!munnari.oz.au!hp9000.csc.cuhk.hk!uxmail!uxmail.ust.hk!eekhfung

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Newsgroups: comp.lang.verilog
Path: arc1-ca.pugleaf.net!sparky!uunet!munnari.oz.au!hp9000.csc.cuhk.hk!uxmail!uxmail.ust.hk!eekhfung
From: eekhfung@uxmail.ust.hk (Fung Ka Hing)
Subject: Analogue modeling by Verilog
Message-ID: <1992Sep3.071552.9412@uxmail.ust.hk>
Summary: Enquiry for information
Sender: eekhfung@hkust.hk
Organization: Hong Kong University of Science and Technology
Date: Thu, 3 Sep 1992 07:15:52 GMT
Lines: 4