Article View: comp.lang.verilog
Article #106Implicit type conversion
From: Ken Hanson
Date: Tue, 13 Oct 1992 16:34
Date: Tue, 13 Oct 1992 16:34
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The Verilog manuals don't go into much detail regarding type conversion, except regarding reg vectors and signed values. What are the rules regarding implicit type conversion. As far as I can tell whenever a reg is involved in an expression, the evaluation is in unsigned arithmetic, regardless of the other operands type. What about real types? Are they always converted to unsigned ints? Any answers to the above questions would be much appreciated! -- Ken (hanson@henson.cc.wwu.edu)
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Path: arc1-ca.pugleaf.net!sparky!uunet!ogicse!henson!hanson From: hanson@henson.cc.wwu.edu (Ken Hanson) Newsgroups: comp.lang.verilog Subject: Implicit type conversion Summary: Implicit type conversion in verilog? Keywords: verilog, types, expressions Message-ID: <1992Oct13.163435.118@henson.cc.wwu.edu> Date: 13 Oct 92 16:34:35 GMT Article-I.D.: henson.1992Oct13.163435.118 Organization: Western Washington University Lines: 9