Article View: comp.lang.verilog
Article #107Re: emacs verilog-mode bug report
From: Richard Eversole; x6239
Date: Mon, 12 Oct 1992 13:22
Date: Mon, 12 Oct 1992 13:22
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1626 bytes
In article <1992Sep25.204723.11454@oakhill.sps.mot.com>, johnw@oakhill.sps.mot.com (John Waite) writes:
|> I have tried to indent lines with an "else" on them but
|> verilog-mode gets confused and hangs up.
|>
|> There may also be a problem with too many levels of
|> "begin/end"'s; there comes a point where verilog mode
|> does not find the previous level (or something like
|> that) and aligns the "end" with the previous "begin".
|>
How many levels of else ?
I got the patches for indent mode from Michio Hayakawa and
applied them but have not had time to fully check them out.
You are using my verilog mode ?
Current version is 3.1
In any event, the bug has been noted and when I get a chance to get
back to working on it I'll look at it more carefully.
|> Cheers,
|> --
|> John Waite AMCU Modular Microcontrollers
|> Motorola, Inc. Systems Design
|> Mail Stop OE-320
|> 6501 William Cannon Dr. West
--
=====================================================================
eversole@cadence.com
Live long and prosper !
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Newsgroups: comp.lang.verilog Path: arc1-ca.pugleaf.net!sparky!uunet!Cadence.COM!acae037!eversole From: eversole@acae037.cadence.com (Richard Eversole; x6239) Subject: Re: emacs verilog-mode bug report Message-ID: <1992Oct12.132231.22056@Cadence.COM> Sender: usenet@Cadence.COM (Usenet News) Nntp-Posting-Host: acae037 Reply-To: eversole@acae037.cadence.com (Richard Eversole; x6239) Organization: Cadence Design Systems, Inc. References: <1992Sep25.204723.11454@oakhill.sps.mot.com> Date: Mon, 12 Oct 1992 13:22:31 GMT Lines: 34