🚀 go-pugleaf

We are very new users of verilog and are having trouble with a few
things .. any experts out there can help ???

1. We *had* this kind of code :-

   module mod_name (in,control,data) ;
   input in,control ;
   inout data ;

   reg out_buf ;

   assign data = (control) out_buf ? 1'bz ;

   out_buf = ......

And so on. Data was a bi-directional port used both as an input and an
output. This compiles OK.

NOW ... we tried to use a specify block to set module delays ...and
tried something like ...

   module mod_name (in,control,data) ;
   input in,control ;
   inout data ;

   reg out_buf ;

   bufif1 b1 (data,out_buf,control) ; 

   out_buf = ......
  
  specify
    (in *> data) = (x,y,z etc.) ;
  endspecify

When I try to compile this it gives an error indicating that 'data'
has to be acceleratable ...... 

Isn't "inout" acceleratable ????? Or is it something to do with bufif1
??  I've done as similar thing using data as an output with a norma
buf and that works OK. How do I get round this ???


2) Related to the above scenario. If I want to output buffer a bus how
do I do it without needing to buffer each individal bit ?

ie    1-bit ... buf(out,in)

but   n-bit     buf(out[n-1],in[n-1])
                buf(out[n-2],in[n-2])
                  ...
                  ...
                buf(out[0],in[0])

Thanks in advance for any advice.

Gary Cook.

ps. Exuse the .signature .... I normally only submit to rec.sport.soccer !

--
  Gary Cook,                  LL      UU   UU   FFFFFF   CCCCCC             
  BNR Europe Limited.          LL      UU   UU   FF       CC   
  Harlow,                       LL      UU   UU   FFFFFF   CC                
  England.                       LL      UU   UU   FF       CC               
  E-Mail : grc@bnr.co.uk          LLLLL   UUUUUUU   FF       CCCCCC